As the geometries of semiconductor devices and particularly MOS transistors are being scaled to continually shorter gate lengths, there is a requirement for reduction in short channel effects. It is known that these short channel effects can be reduced by the use of non-uniform doping levels in the channel region. One manner of obtaining such non-uniform doping levels in the channel region has been by the use of pocket or halo implants. Both a pocket and a halo implant involve, in addition to the standard source/drain implant, the introduction of an implant which is at an angle of from about 10 to about 80 degrees and preferably about 30 to 40 degrees relative to a normal to the substrate surface. The pocket or halo implant is of opposite conductivity type to that of the source/drain region, is directed partially under the gate electrode and uses the gate electrode as a mask. In this manner, a pocket or halo region is formed which abuts the source/drain region as well as the gate oxide, is within the channel region and extends under the gate electrode, to provide a region between the source/drain and the channel which is more highly doped than the channel region and of like conductivity type.
In an optimal situation, it would be desirable to place the pocket or halo region at least partially under the gate and below the surface of the substrate proximate the source/drain regions. Unfortunately, the pocket and halo depth and doping levels cannot be controlled enough as to precisely place the pocket or halo region in this desired location. For example, because of the present angled Halo process used (of which will be detailed with respect to FIG. 1A below) a substantial portion of the pocket or halo region is located at a surface of the substrate and between the two source/drain regions in the channel region. This location, however, affects the channel mobility of the device, and especially as it attempts to shut off the subsurface current. For this reason, present pocket and halo implants are either not used at all or are used in moderation to minimize the problems inherent in the presence of the pocket or halo implant region in the channel region between the source/drain regions.
A typical process flow as used in the prior art to fabricate a MOS transistor having a pocket or halo implant is shown with reference to FIG. 1A, wherein there is provided a substrate 110 of semiconductor material, such as, for example, silicon, onto which has been formed, in a standard manner, such as by thermal growth or chemical vapor deposition (CVD), a layer of silicon dioxide 120. A polysilicon gate 130 is formed over the silicon dioxide layer 120 in a standard manner, such as by deposition of polysilicon over the silicon dioxide layer 120 with subsequent patterning and etching to form the gate structure 130. At this time, an optional screen oxide can be formed, either thermally or deposited.
Thereafter, a lightly doped drain (LDD) to moderately doped drain (MDD) is formed, generally by a simple ion implantation of phosphorus and/or arsenic for n-channel and boron for p-channel with doses in the range from about 1E13 to about 1E15 atoms/cm2 for LDD to MDD and with an incidence usually near normal to the surface plane. The pocket or halo 140 is then implanted, this being an ion implantation of the same conductivity type as the substrate and opposite conductivity type to the LDD/MDD with lesser doses in the range from about 1E12 to about 1E14 atoms/cm2 with incidence angles usually equal to or greater than the LDD/MDD implantation and possibly rotated about an axis perpendicular to the surface using the gate 130 as a mask. An optional anneal can take place at this point to limit transient enhanced diffusion (TED). A sidewall spacer 150 may then be formed in a standard manner, generally of silicon dioxide, silicon nitride or a combination of silicon dioxide and silicon nitride. Thereafter, source/drain regions 160 may be formed within the substrate 110. Generally, the source/drain regions 160 include doses of about 1E15 atoms/cm2, which are of opposite conductivity type to the pocket or halo implant 140. An optional anneal may be conducted thereafter to activate the dopant. With the subsequent annealing, the source/drain regions 160 are formed with the pocket implant 140 extending thereunder, as well as under the gate 130, to isolate the source/drain regions 160 from the channel 170 as shown in FIG. 1A.
Turning now briefly to FIG. 1B, illustrated is a process simulation image 180 of a semiconductor device similar to the semiconductor device 100 illustrated in FIG. 1A. Notice how the pocket or halo implants 185 are located at a surface of the substrate 190 in the channel region 195 thereof.
Accordingly, what is needed in the art is a semiconductor device and method of manufacture therefor, that does not encounter the pocket or halo implant issues experienced by the prior art structures.